The general area of the present invention is digital logic circuits for the generation and detection of parity and specific area of the present invention is a logic structure for high speed parity generation and detection utilizing Complementary Metal Oxide Semiconductor (CMOS) technology.
Examples of prior art parity generation/detection logic circuits are Texas Instruments, Inc. types SN54LS280, SN54S280, SN74LS280 and SN74S280. The functional block diagram for these 9 bit odd/even parity generators/checkers is shown at page 7-409 of the TTL Data Book for Design Engineers, Second Edition, Copyright 1976 Texas Instruments, Inc. These particular parity generation/detection circuits utilize seven levels of logic elements, with attendant delay. The processes within each of the seven levels are isolation (and inversion), inversion, ANDing in AND gates, collecting in OR gates, inversion, ANDing in AND gates, and collecting in OR gates. The number of levels is, of course, a function of the number of input bits (9 for the TI circuit). The important aspect to note, for purposes of the present invention, is the necessity of inversion between the various collector stages of each level.
Recognition of the problem of long operational times arising from the multiplicity of logic levels within prior art circuits is evidenced in the discussion of a Cascode Parity Circuit by E. L. Carter and H. T. Ward at Vol. 24, No. 3, August, 1981, IBM Technical Disclosure Bulletin. Such Cascode Parity Circuit, as constructed in emitter coupled logic (ECL) and limited by the adequacy of supply and signal voltages, is an attempt, for a small number of inputs, to generate or detect parity without the use of conventional unit logic blocks (e.g., AND-Invert logic as in the TI circuits) and at enhanced speeds.